• DocumentCode
    1537958
  • Title

    BIST test pattern generator for delay testing

  • Author

    Girard, P. ; Landrault, C. ; Moréda, V. ; Pravossoudovitch, S.

  • Author_Institution
    Lab. d´´Inf. de Robotique et de Microelectron., CNRS, Montpellier, France
  • Volume
    33
  • Issue
    17
  • fYear
    1997
  • fDate
    8/14/1997 12:00:00 AM
  • Firstpage
    1429
  • Lastpage
    1431
  • Abstract
    To detect delay faults in a digital circuit requires a test sequence applied at the nominal frequency of the circuit. Built-in self-test (BIST) is a technique that provides such testing possibilities at speed, without expensive test equipments. A BIST test pattern generator (TPG) design, targeting the detection of delay faults is proposed
  • Keywords
    automatic testing; built-in self test; delays; digital integrated circuits; fault location; integrated circuit testing; logic testing; BIST; built-in self-test; delay fault detection; delay testing; digital circuit; test pattern generator;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19970998
  • Filename
    621616
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1537958