A 30-MHz hybrid analog/digital clock recovery circuit in 2-μm CMOS

Author

Kim, Beomsup ; Helman, David N. ; Gray, Paul R.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

25

Issue

6

fYear

1990

fDate

12/1/1990 12:00:00 AM

Firstpage

1385

Lastpage

1394

Abstract

A high-speed hybrid clock recovery circuit composed of an analog phase-locked loop (PLL) and a digital PLL (DPLL) for disk drive applications is described. The chip operates at a maximum data rate of 33 MHz from a single 5-V power supply and achieves fast acquisition, a decode window of 95% of full window width, effective sampling jitter of 100-ps rms, and an effective input sampling rate of 1 GHz. The ring oscillator in the analog PLL shows a 62 p.p.m./°C temperature coefficient (TC) and 4.5%/V supply sensitivity of free-running frequency. The total power dissipation is about 600 mW, and the active area is 30000 mil² in a 2-μm single-poly double-metal n-well CMOS process

Keywords

CMOS integrated circuits; clocks; magnetic disc storage; phase-locked loops; 2 micron; 30 MHz; CMOS; active area; analog phase-locked loop; data rate; decode window; digital PLL; disk drive applications; double-metal n-well CMOS process; effective input sampling rate; effective sampling jitter; fast acquisition; free-running frequency; hybrid analog/digital clock recovery circuit; ring oscillator; total power dissipation; Circuits; Clocks; Decoding; Disk drives; Jitter; Phase locked loops; Power supplies; Ring oscillators; Sampling methods; Temperature sensors;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.62166

Filename

62166