• DocumentCode
    1539011
  • Title

    High performance RISC microprocessors

  • Author

    Choquette, Jack ; Gupta, Mayank ; McCarthy, Dominic ; Veenstra, Jack

  • Author_Institution
    SandCraft Inc., Santa Clara, CA, USA
  • Volume
    19
  • Issue
    4
  • fYear
    1999
  • Firstpage
    48
  • Lastpage
    55
  • Abstract
    Many embedded systems and consumer appliances require high performance at extremely low price points, and they need them yesterday! Meeting these needs is the latest challenge for system and processor architects. SandCraft recognized this challenge early on and developed the Montage architecture to meet these needs and generate revenue that fuels business growth. Montage implements MIPS-compatible processors for license to MIPS licensees. We have implemented two Montage incarnations now on the market: the SR1 and the SR1-GX high-performance microprocessor cores. Other designs are in the pipeline. With the intellectual property in place, the architecture will proliferate and show that low cost and flexibility do not have to come at the cost of compromising performance. Here, we describe the philosophy behind the development of the Montage architecture and illustrate some of the thinking that resulted in this processor line
  • Keywords
    embedded systems; microprocessor chips; reduced instruction set computing; Montage architecture; SR1; SR1-GX; consumer appliances; embedded systems; high performance RISC microprocessors; Coprocessors; Costs; Embedded system; Home appliances; Integrated circuit modeling; Intellectual property; Lifting equipment; Microprocessors; Pipelines; Reduced instruction set computing;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/40.782567
  • Filename
    782567