Dynamic GaAs capacitively coupled domino logic (CCDL)

Author

Hoe, David H K ; Salama, C. Andre T

Author_Institution

Dept. of Electr. Eng., Toronto Univ., Ont., Canada

Volume

26

Issue

6

fYear

1991

fDate

6/1/1991 12:00:00 AM

Firstpage

844

Lastpage

849

Abstract

Dynamic capacitively coupled domino logic (CCDL) has been proposed as a practical means of implementing low-power and high-speed complex gates. The CCDL gate delay characteristics obtained from an analytical model and from test circuits implemented in a 1-μm GaAs E/D process are presented. In addition, the feasibility of using CCDL gates to implement practical circuits is demonstrated by the experimental characterization of a 4-b carry-lookahead adder. The adder has a critical delay of 1.1 ns and a power dissipation of 96 mW. A comparison of the dynamic CCDL adder with conventional static designs indicates the advantages of dynamic CCDL gates in reducing power dissipation and increasing speed, making such gates suitable for VLSI implementations

Keywords

III-V semiconductors; VLSI; adders; carry logic; gallium arsenide; integrated logic circuits; logic gates; 1 micron; 1.1 ns; 96 mW; E/D process; VLSI; analytical model; capacitively coupled domino logic; carry-lookahead adder; gate delay characteristics; high-speed complex gates; power dissipation; speed; Adders; Circuit testing; Delay; FETs; Gallium arsenide; Inverters; Logic circuits; Logic devices; MIM capacitors; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.78273

Filename

78273