Mixed digital/analog signal processing for a single-chip 2B1Q U -interface transceiver

Mixed analog-digital signal processing aspects of a 5-V single-chip U-interface 2B1Q transceiver are discussed. Analog signal processing preconditions the signal by reducing jitter-induced echo and nonlinear echo components, and by maximizing the dynamic range utilization of the 13-b analog-to-digital (A/D) converter. The digital signal processor performs the high-pass filtering, precursor equalization, linear echo cancellation, far-end signal equalization, and timing recovery functions. The analog signal preconditioning technique allows the entire digital signal processing (DSP) section to be designed without a single dedicated multiplier. The U-interface transceiver has been realized in a 1.5-μm double-metal CMOS process, resulting in a circuit area of 77 mm². Total power consumption is 300 mW. To comply with the ANSI-specified performance test procedures, a crosstalk noise generator and injection circuit were custom built along with a jitter generation system, all of which match the ANSI noise and jitter templates. Testing was performed over the 15 ANSI loops and countless other random configurations. Full compliance with the standard protocol and timing limits was achieved on all the loops