Title :
Low test-application time method for EEPLA testing
Author :
Wei, K.-C. ; Liu, B.-D. ; Tang, J.J.
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fDate :
1/1/1997 12:00:00 AM
Abstract :
An efficient method for EEPLA testing is presented. In this method the authors propose an interleave programming algorithm for the EEPLA to enhance the controllability of the OR plane and the observability of the AND plane during the testing of EEPLA. The salient features of this method are: (i) low overhead, (ii) high fault coverage, (iii) simple test set, and (iv) low test-application time. Using this method, all multiple stuck-at faults, multiple crosspoint faults and all multiple bridging faults can be detected
Keywords :
controllability; logic testing; observability; programmable logic arrays; AND plane; EEPLA testing; OR plane; controllability; high fault coverage; interleave programming algorithm; low overhead; low test application time method; low test-application time; multiple bridging faults; multiple crosspoint faults; multiple stuck-at faults; observability; simple test set;
Journal_Title :
Computers and Digital Techniques, IEE Proceedings -
DOI :
10.1049/ip-cdt:19970636