DocumentCode :
1539856
Title :
Carry delayed save adders for computing the product A.B modulo N in log2 N steps
Author :
Forster, C.H.N. ; Dlay, S.S. ; Gorgui-Naguib, R.N.
Author_Institution :
Dept. of Electr. & Electron. Eng., Newcastle upon Tyne, UK
Volume :
26
Issue :
18
fYear :
1990
Firstpage :
1544
Lastpage :
1545
Abstract :
The design of a new modular multiplier which uses carry delayed save adders is presented. The system makes use of the techniques of sign estimation and digital division from the right in order to produce the product in n steps. The inputs to the device can be in carry save, delayed save or standard binary and the output is produced as a delayed save integer. This means that the system is ideal for use in situations where the product produced by the previous operation is then fed back to be re-multiplied, e.g. repeated squaring and exponentiation.
Keywords :
adders; digital arithmetic; multiplying circuits; VLSI; carry delayed save adders; cryptography; delayed save integer; digital division; exponentiation; modular multiplier; sign estimation; squaring;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:19900991
Filename :
58145
Link To Document :
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