Analysis and comparison of variations in double edge triggered flip-flops

In this paper, the impact of variations on the most representative double-edge triggered flip-flop (FF) topologies is comparatively evaluated in 65-nm CMOS. The analysis explicitly considers fundamental sources of variations such as process, voltage and temperature (PVT) variations. For each FF topology, the variations of the performance, the energy per cycle and the leakage power are statistically evaluated through Monte Carlo simulations. The analysis explicitly includes the important impact of layout parasitics in different respects. First, they are accounted for in the circuit optimization loop, rather than being considered an afterthought. In addition, interconnect variations are explicitly considered in the statistical characterization of the flip-flops. Results for the different FF topologies are compared to identify the potential advantages and drawbacks of each topology. To gain an insight into the impact of transistor sizing and load, each FF topology is analyzed under a wide range of design targets and loads. The conclusions of the analysis are a useful tool to assist the designer in the preliminary variation budgeting before detailed circuit design, as well as in selecting the most appropriate topology for a targeted application.