SRAM write margin cell estimation using wordline modulation and read/write operations

A new writability metric is proposed to estimate the write margin using regular read and write access to 6T CMOS SRAM cells. The metric is obtained with a fully digital way and is compared with others methods based on the measure of the bit-line current while word-line or the bit-line voltages are being swept. A good correlation between proposed and previous metrics is demonstrated. The proposed metric estimates the writability margin regular read/write operations. Therefore, the memory cell array is not modified allowing to monitor the SRAM cell writability characterization evolution during memory lifetime.