Variability characterisation of nanoscale Si and InGaAs FinFETs at subthreshold

We have simulated two nanoscaled Fin-FET devices with different body material (InGaAs and Si) in order to analyse the effect of the Line Edge Roughness (LER) and Metal Gate Workfunction (MGW) variabilities. We have used a workload manager to deploy the simulations and to collect the data across diferent computational infrastructures. We have found that for most of the figures of merit, the InGaAs device has more tolerance to these variability sources inside the scope that we actually studied. Also, the MGW has larger impact than the LER variability in both devices, 14% more for InGaAs and 33% more for Si. We have also found larger correlation between the values of threshold voltage for low and high drain bias in the case of InGaAs than of Si, denoting a drastical difference in the behaviour of both devices.