Title :
Decimation filter with novel MVTL XOR gate
Author :
Xie, Y.P. ; Van Duzer, T.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fDate :
6/1/1997 12:00:00 AM
Abstract :
A single-rail Modified Variable Threshold Logic (MVTL) decimation filter is designed by employing a novel XOR gate, which overcomes the difficulty of the lack of a good inverter in the MVTL logic family. A 10-bit deep-pipelined decimation filter consisting of about 700 junctions in a 5 mm/spl times/5 mm chip with power consumption of 0.4 mW is designed.
Keywords :
FIR filters; logic gates; pipeline processing; superconducting logic circuits; threshold logic; 0.4 mW; FIR decimation filter; MVTL XOR gate; deep-pipelined decimation filter; power consumption; single-rail modified variable threshold logic decimation filter; Clocks; Delay; Discrete wavelet transforms; Feeds; Pipelines; Rails; Resistors; Roentgenium; Superconducting filters; Switches;
Journal_Title :
Applied Superconductivity, IEEE Transactions on
