DocumentCode
1540543
Title
An 8-b 800-MHz DAC
Author
Nojima, Kazuhisa ; Gendai, Yuji
Author_Institution
Sony Corp., Kanagawa, Japan
Volume
25
Issue
6
fYear
1990
fDate
12/1/1990 12:00:00 AM
Firstpage
1353
Lastpage
1359
Abstract
An 8-b video DAC which performs conversions at 800 MHz is reported. A double poly-Si emitter self-aligned process and a 64-b MSB (most significant bit) range are used. A multiple-level emitter-coupled logic MEL decoder circuit and multiplexed data inputs are used to enhance the speed and to lower the glitch impulse. Rise and fall times are less than 380 ps for high-speed operation. Power dissipation is 750 mW with a -4.5-V supply voltage
Keywords
bipolar integrated circuits; digital-analogue conversion; emitter-coupled logic; 4.5 V; 750 mW; MSB; double poly-Si emitter self-aligned process; fall times; glitch impulse; high-speed operation; multiple-level emitter-coupled logic MEL decoder circuit; multiplexed data inputs; rise times; video DAC; Application software; Binary codes; Computer displays; Computer graphics; Decoding; Linearity; Logic circuits; Power dissipation; Silicon; Switches;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.62179
Filename
62179
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