Title :
Junction leakage current degradation under the off-state bias-temperature stress: a new reliability assessment method for high-density DRAMs
Author :
Young Pil Kim ; Sung Tae Kim ; Moon, Joo ; Kim, Sang U.
Author_Institution :
Semicond. R&D Center, Samsung Electron. Co. Ltd., Kyonggi, South Korea
fDate :
6/1/2001 12:00:00 AM
Abstract :
A new reliability assessment method on retention time failure for high-density DRAMs under off-state bias-temperature (B-T) stress was suggested and investigated using the well-known gated-diode test pattern. The transistor junction leakage current degradation, total junction leakage current especially including gate-induced drain leakage (GIDL) component, under the off-state B-T stress was found to be more sensitive than widely-used gate-oxide degradation under the Fowler-Nordheim (F-N) tunneling stress. The off-state bias stress also gives significantly higher degradation on the gate-oxide stress-induced leakage current (SILC) than F-N tunneling current stress. The features of the off-state B-T stress which gives stress to almost all transistor leakage components and the mechanism of the junction leakage current degradation under the off-state bias condition were discussed
Keywords :
DRAM chips; failure analysis; integrated circuit reliability; integrated circuit testing; leakage currents; GIDL component; gate-induced drain leakage component; gate-oxide SILC; gated-diode test pattern; high-density DRAMs; junction leakage current degradation; off-state bias-temperature stress; reliability assessment method; retention time failure; stress-induced leakage current; total junction leakage current; transistor junction leakage current; Condition monitoring; Current measurement; Degradation; Dielectric measurements; Leakage current; P-n junctions; Random access memory; Stress measurement; Testing; Tunneling;
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
DOI :
10.1109/7298.956703