DocumentCode
1541193
Title
Optimization of placement by candidate sieving
Author
Takagi, Makoto
Author_Institution
A&I Syst. Co. Ltd., Chiba, Japan
Volume
24
Issue
3
fYear
2001
fDate
7/1/2001 12:00:00 AM
Firstpage
178
Lastpage
187
Abstract
A new algorithm for standard cell placement problem is presented. It is based on an idea that appropriate step by step reduction of allocatable cells for each component yields a good placement result. This algorithm named candidate sieving is applicable for discrete quadratic assignment problem with some constraint. The results obtained by candidate sieving are compared in terms of wire length and computing time with those obtained by simulated annealing which is considered the most popular method today. In many cases, candidate sieving has yielded shorter wire lengths, which are equal or almost equal to those obtained by simulated annealing, but with much less computing time
Keywords
cellular arrays; circuit layout CAD; circuit optimisation; integrated circuit layout; logic CAD; simulated annealing; allocatable cells; candidate sieving; computing time; discrete quadratic assignment problem; placement optimisation; simulated annealing; standard cell; wire length; Cities and towns; Computational modeling; Crops; Genetic algorithms; Linear approximation; Partitioning algorithms; Polynomials; Simulated annealing; Very large scale integration; Wire;
fLanguage
English
Journal_Title
Electronics Packaging Manufacturing, IEEE Transactions on
Publisher
ieee
ISSN
1521-334X
Type
jour
DOI
10.1109/6104.956803
Filename
956803
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