DocumentCode :
154150
Title :
Hydra: Efficient Detection of Multiple Concurrency Bugs on Fused CPU-GPU Architecture
Author :
Zhuofang Dai ; Haojun Wang ; Weihua Zhang ; Haibo Chen ; Binyu Zang
Author_Institution :
Software Sch., Fudan Univ., Shanghai, China
fYear :
2014
fDate :
9-12 Sept. 2014
Firstpage :
331
Lastpage :
340
Abstract :
Detecting concurrency bugs, such as data race, atomicity violation and order violation, is a cumbersome task for programmers. This situation is further being exacerbated due to the increasing number of cores in a single machine and the prevalence of threaded programming models. Unfortunately, many existing software-based approaches usually incur high runtime overhead or accuracy loss, while most hardware-based proposals usually focus on a specific type of bugs and thus are inflexible to detect a variety of concurrency bugs. In this paper, we propose Hydra, an approach that leverages massive parallelism and programmability of fused GPU architecture to simultaneously detect multiple types of concurrency bugs, including data race, atomicity violation and order violation. Hydra instruments and collects program behavior on CPU and transfers the traces to GPU for bug detection through on-chip interconnect. Furthermore, to achieve high speed, Hydra exploits bloom filter to filter out unnecessary detection traces. Hydra incurs small hardware complexity and requires no changes to internal critical-path processor components such as cache and its coherence protocol, and is with about 1.1% hardware overhead under a 32-core configuration. Experimental results show that Hydra only introduces about 0.35% overhead on average for detecting one type of bugs and 0.92% overhead for simultaneously detecting multiple bugs, yet with the similar detectability of a heavyweight software bug detector (e.g., Helgrind).
Keywords :
graphics processing units; program debugging; Helgrind; Hydra; atomicity violation; bloom filter; bug detection; cache; critical-path processor component; data race; fused CPU-GPU architecture; heavyweight software bug detector; massive parallelism; multiple concurrency bugs; on-chip interconnect; order violation; software-based approach; Computer bugs; Concurrent computing; Graphics processing units; History; Image color analysis; Instruction sets; Synchronization; concurrency bug; debugging; gpu;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Processing (ICPP), 2014 43rd International Conference on
Conference_Location :
Minneapolis MN
ISSN :
0190-3918
Type :
conf
DOI :
10.1109/ICPP.2014.42
Filename :
6957242
Link To Document :
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