DocumentCode :
154176
Title :
Lightweight Software Transactions on GPUs
Author :
Holey, Anup ; Zhai, Antonia
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of Minnesota, Minneapolis, MN, USA
fYear :
2014
fDate :
9-12 Sept. 2014
Firstpage :
461
Lastpage :
470
Abstract :
Graphics Processing Units (GPUs) provide an attractive option for extracting data-level parallelism from diverse applications. However, some applications, although possess abundant data-level parallelism, exhibit irregular memory access patterns to the shared data structures. Porting such applications to GPUs requires synchronization mechanisms such as locks, which significantly increase the programming complexity. Coarse-grained locking, where a single lock controls all the shared resources, although reduces programming efforts, can substantially serialize GPU threads. On the other hand, fine-grained locking, where each data element is protected by an independent lock, although facilitates maximum parallelism, requires significant programming efforts. To overcome these challenges, we propose to support software transactional memory (STM) on GPU that is able to achieve performance comparable to fine-grained locking, while requiring minimal programming efforts. Software-based transactional execution can incur significant runtime overheads due to activities such as detecting conflicts across thousands of GPU threads and managing a consistent memory state. Thus, in this paper we illustrate three lightweight STM designs that are capable of scaling to a large number of GPU threads. In our system, programmers simply mark the critical sections in the applications, and the underlying STM support is able to achieve performance comparable to fine-grained locking.
Keywords :
data structures; graphics processing units; multi-threading; parallel processing; storage management; transaction processing; GPU threads; GPUs; STM; application porting; coarse-grained locking; consistent memory state management; data-level parallelism; graphics processing units; irregular memory access patterns; programming complexity; shared data structures; software transactional memory; software transactions; software-based transactional execution; synchronization mechanisms; Graphics processing units; Instruction sets; Parallel processing; Programming; Reactive power; System recovery; GPUs; parallel programming; software transactional memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Processing (ICPP), 2014 43rd International Conference on
Conference_Location :
Minneapolis MN
ISSN :
0190-3918
Type :
conf
DOI :
10.1109/ICPP.2014.55
Filename :
6957255
Link To Document :
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