3D sequential integration opportunities and technology optimization

Author

Batude, P. ; Sklenard, B. ; Fenouillet-Beranger, C. ; Previtali, B. ; Tabone, C. ; Rozeau, O. ; Billoint, O. ; Turkyilmaz, O. ; Sarhan, H. ; Thuries, S. ; Cibrario, G. ; Brunet, L. ; Deprat, F. ; Michallet, J.-E. ; Clermidy, F. ; Vinet, M.

Author_Institution

CEA-leti, Minatec, Grenoble, France

fYear

2014

fDate

20-23 May 2014

Firstpage

373

Lastpage

376

Abstract

Compared with TSV-based 3D ICs, monolithic or sequential 3D ICs presents “true” benefits of going to the vertical dimension as the stacked layers can be connected at the transistor scale. The high versatility of this technology is evidenced via several examples requiring small 3D contact pitch. Monolithic 3D is shown to enable substantial gain in area and performance as compared to planar technology without scaling the transistor technology node. This paper summarizes the technological challenges of this concept: it offers a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity.

Keywords

circuit optimisation; three-dimensional integrated circuits; 3D sequential integration; TSV-based 3D ICs; bottom MOSFET integrity; high performance low temperature top transistor; monolithic 3D ICs; planar technology; sequential 3D ICs; small 3D contact pitch; stacked layers; technology optimization; transistor scale; vertical dimension; Annealing; CMOS integrated circuits; Field effect transistors; Performance evaluation; Silicon; Three-dimensional displays;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC), 2014 IEEE International

Conference_Location

San Jose, CA

Print_ISBN

978-1-4799-5016-4

Type

conf

DOI

10.1109/IITC.2014.6831837

Filename

6831837