Exploiting CMOS Technology to Enhance the Performance of ISFET Sensors

This letter presents a novel method for fabricating ion-sensitive field-effect transistor (ISFET) devices in unmodified CMOS technologies. Conventional CMOS ISFETs utilize the protective passivation coating as the sensing membrane, with the sensed potential being coupled down to the floating MOS gate via a stack of conducting and insulating layers. The proposed structure minimizes the use of these layers by exploiting the passivation-opening mask, normally intended for bond-pad openings. Parasitic effects such as reduced transconductance and trapped charge within the floating gate structure are minimized, resulting in a lower VT and improved chemical transconductance efficiency. Other characteristics, including chemical sensitivity, reference leakage current, and noise power, are at comparable levels with conventional CMOS-based ISFET devices.