Overview of embedded packaging technologies

Summary form only given. Moore´s law has been the foundation for increasing complexity and density of semiconductor chips and has prevailed over the years through many transitions in silicon (Si) nodes. The simultaneous scaling of density, cost and performance which is made possible by fan-out wafer level packaging may be viewed as the manifestation of Moore´s law in the packaging domain. Recent developments in Fan-out Wafer level technology (also known as embedded Wafer Level Ball Grid Array, or eWLB) at STATS ChipPAC ranging from package architecture, volume manufacturing processes, as well as comprehensive methodologies for defining the optimum application space for the packaging technology over competing options will be presented. Novel integration schemes comprising multi-die, 2.5D and 3D face-to-face configurations will be presented that enable a quantum leap in performance and form factor while being cost competitive to other alternative options such as Through Silicon Via (TSV). The proliferation of the application space from traditional RF and Base Band devices in Mobile products to more advanced Application Processors and larger packages in the computing space will be presented. The future direction for this technology, including new paradigms in manufacturing processes, will also be discussed.