Through-silicon-via material property variation impact on full-chip reliability and timing

Author

Moongon Jung ; Pan, David Z. ; Sung Kyu Lim

Author_Institution

Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2014

fDate

20-23 May 2014

Firstpage

105

Lastpage

108

Abstract

We study the impact of material property variations in through-silicon-via (TSV) and its surrounding structures on the reliability and performance of 3D ICs. We focus on coefficient of thermal expansion (CTE) and Young´s modulus variations for TSV, barrier, and liner materials. Our toolset efficiently handles the complexity of modeling and analysis of individual TSVs as well as full-chip 3D IC designs. This tool enables 3D IC designers to accurately assess and evaluate various methods to tolerate mechanical reliability and performance variations.

Keywords

Young´s modulus; integrated circuit design; integrated circuit modelling; integrated circuit reliability; thermal expansion; three-dimensional integrated circuits; CTE; TSV; Young´s modulus; coefficient of thermal expansion; full-chip 3D IC designs; full-chip reliability; mechanical reliability; through-silicon-via material property variation; Educational institutions; Reliability; Stress; Substrates; Thermal analysis; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC), 2014 IEEE International

Conference_Location

San Jose, CA

Print_ISBN

978-1-4799-5016-4

Type

conf

DOI

10.1109/IITC.2014.6831846

Filename

6831846