Reliability analysis of bumping schemes under chip package interaction

Author

Kappaganthu, Sri Ramakanth ; Karmarkar, Aditya ; Xiaopeng Xu ; El Sayed, K. ; Avci, I. ; Chawla, Vikas ; Mishra, Bud ; Kucherov, Andrey ; Weixing Zhou ; Johnson, Mark ; Balasingam, P.

Author_Institution

Synopsys (India) Private Ltd., Hyderabad, India

fYear

2014

fDate

20-23 May 2014

Firstpage

151

Lastpage

154

Abstract

Reliability analysis for three bumping configurations is performed under typical chip package interaction. A sequential submodeling technique is employed to capture stress evolution during entire package assembly process. Mechanical stresses are assessed in various regions around bumps to determine the optimal bumping scheme with the minimal reliability risk. Underfill material property impact on package reliability is also examined. This study provides important guidelines to design robust bumping configurations with fine-tuned material properties.

Keywords

chip scale packaging; fine-pitch technology; reliability; stress analysis; bumping schemes; chip package interaction; fine-tuned material properties; mechanical stress; package assembly process; reliability analysis; sequential submodeling technique; stress evolution; Copper; Material properties; Reliability engineering; Soldering; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC), 2014 IEEE International

Conference_Location

San Jose, CA

Print_ISBN

978-1-4799-5016-4

Type

conf

DOI

10.1109/IITC.2014.6831850

Filename

6831850