Title :
A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM
Author :
Takeshima, Toshio ; Takada, Masahide ; Koike, Hiroki ; Watanabe, Hiroshi ; Koshimaru, Shigeru ; Mitake, Kenjiro ; Kikuchi, Wataru ; Tanigawa, Takaho ; Murotani, Tatsunori ; Noda, Kenji ; Tasaka, Kazuhiro ; Yamanaka, Koji ; Koyama, Kuniaki
Author_Institution :
NEC Corp., Kanagawa, Japan
fDate :
8/1/1990 12:00:00 AM
Abstract :
A single 5-V power supply 16-Mb dynamic random-access memory (DRAM) has been developed using high-speed latched sensing and a built-in self-test (BIST) function with a microprogrammed ROM, in which automatic test pattern generation procedures were stored by microcoded programs. The chip was designed using a double-level Al wiring, 0.55-μm CMOS technology. As a result, a 16-Mb CMOS DRAM with 55-ns typical access time and 130-mm2 chip area was attained by implementing 4.05-μm2 storage cells. The installed ROM was composed of 18 words×10 b, where the marching test and checkerboard scan write/read test procedures were stored, resulting in successful self-test operation. As the BIST circuit occupies 1 mm2 and the area overhead is about 1%, it proves to be promising for large-scale DRAMs
Keywords :
CMOS integrated circuits; automatic testing; integrated circuit testing; integrated memory circuits; random-access storage; read-only storage; 0.55 micron; 16 Mbit; 5 V; 55 ns; BIST circuit; CMOS technology; DRAM; Si-Al; automatic test pattern generation; built-in self-test function; checkerboard scan write/read test; double-level Al wiring; dynamic random-access memory; high-speed latched sensing; marching test; microcoded programs; microprogram ROM; single 5-V power supply; Automatic test pattern generation; Automatic testing; Built-in self-test; CMOS technology; Circuit testing; Large-scale systems; Power supplies; Random access memory; Read only memory; Wiring;
Journal_Title :
Solid-State Circuits, IEEE Journal of
