Scaling of digital BiCMOS circuits

Author

Bellaouar, Abdel Latif ; Embabi, Sherif H K ; Elmasry, Mohamed I.

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

Volume

25

Issue

4

fYear

1990

fDate

8/1/1990 12:00:00 AM

Firstpage

932

Lastpage

941

Abstract

A generalized first-order scaling theory for BiCMOS digital circuit structures is presented. The effect of horizontal, vertical, and voltage scaling on the speed performance of various BiCMOS circuits is presented. The generalized scaling theory is used for the MOSFET, and the constant collector current (CIC) scaling scheme is used for the bipolar junction transistor (BJT). In scaling the bipolar transistor, polysilicon emitter contact and bandgap narrowing are taken into account. A case study for scaling BiCMOS circuits operating at 5- and 3.3-V power supplies shows that scaling improved BiCMOS buffers more significantly than CMOS buffers. Moreover, the low delay-to-load sensitivity of BiCMOS is preserved with scaling

Keywords

BIMOS integrated circuits; buffer circuits; digital integrated circuits; integrated circuit technology; 3.3 V; 5 V; BJT; CMOS/ECL convertors; ECL/CMOS convertors; MOSFET; bandgap narrowing; bipolar junction transistor; buffers; constant collector current; digital BiCMOS circuits; first-order scaling theory; horizontal scaling; polysilicon emitter contact; speed performance; voltage scaling; BiCMOS integrated circuits; Bipolar transistors; Delay; Digital circuits; Doping; Electric resistance; Parasitic capacitance; Photonic band gap; Switches; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.58285

Filename

58285