The effect of dielectric relaxation on charge-redistribution A/D converters

The extent to which dielectric relaxation in typical monolithic capacitors degrades the performance of charge-redistribution analog-to-digital (A/D) converters is described. Experimental device data from a monolithic capacitor test circuit are presented, an empirical capacitor model fitted to the measured device performance is described, and simulated A/D system errors are compared with those observed in a monolithic, 10-b, 3.3-μms A/D converter. The agreement found in this comparison demonstrates that the transient error in A/D-converter code transition voltages due to dielectric relaxation may be accurately predicted. The modeling and simulation techniques that are discussed are important tools both for the selection of proper capacitor technology and in the development of circuit designs insensitive to dielectric relaxation. This analysis is also applicable to any circuit where precision is derived from capacitor characteristics, such as sample-and-hold circuits and switched-capacitor filters