A low-inductance, low-I/sub c/ HTS junction process

Author

Murduck, J.M. ; Burch, J. ; Hu, R. ; Pettiette-Hall, C. ; Luine, J.A. ; Schwarzbek, S.M. ; Sergant, M. ; Chan, H.

Author_Institution

TRW Space & Electron. Group, Redondo Beach, CA, USA

Volume

7

Issue

2

fYear

1997

fDate

6/1/1997 12:00:00 AM

Firstpage

2940

Lastpage

2943

Abstract

One of the challenges In fabricating digital circuitry with high temperature superconductors (HTS) is in developing a reliable junction process. The requirements of this junction process include: low-parasitic inductance, well-targeted and reproducible total inductance, uniformity in I/sub c/ and R/sub n/, and also well-targeted I/sub c/ and I/sub c/R/sub n/ product greater than 300 /spl mu/V at 65 K. Junction inductance can be greatly reduced by fabrication above a groundplane. Yet the addition of a groundplane introduces fabrication issues such as film smoothness and maintenance of epitaxy through the multiple layers necessary. Step-edge junctions and SNS edge junctions with groundplanes are examined and compared through a Taguchi experimental design series. Process equipment modifications in our HTS foundry necessary to reach our fabrication goals are outlined.

Keywords

Josephson effect; critical currents; high-temperature superconductors; inductance; HTS junction fabrication; SNS edge junction; Taguchi experimental design; critical current; digital circuit; epitaxy; fabrication; foundry; groundplane; high temperature superconductor; inductance; normal resistance; parasitic inductance; step-edge junction; Critical current; Dielectrics; Digital circuits; Fabrication; High temperature superconductors; Inductance; Logic arrays; Resistors; Silicon; Silver;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/77.621923

Filename

621923