The implementation of digital echo cancellation in codecs

Author

Friedman, Vladimir ; Khoury, John M. ; Theobald, Michael ; Gopal, Venu P.

Author_Institution

AT&T Bell Lab., Murray Hill, NJ, USA

Volume

25

Issue

4

fYear

1990

fDate

8/1/1990 12:00:00 AM

Firstpage

979

Lastpage

986

Abstract

The architecture of a codec in which the echo cancellation is done in two stages, an analog hybrid to reduce the echo level at the input of the A/D converter and a programmable digital balance filter, is presented. The design problems connected with this architecture, such as the signal-to-noise performance of the A/D converter and the limiting effects of the variation of the analog components on the echo cancellation performance of the device and on the structure of the digital balance filters, are discussed. These results were used in the design of a single-power-supply CMOS device implemented in 1.5-μm technology using ΣΔ modulation techniques for A/D and D/A conversion. Its echo cancellation performance is sufficiently high that only one set of coefficients per national standard is necessary

Keywords

CMOS integrated circuits; analogue-digital conversion; codecs; delta modulation; digital filters; digital integrated circuits; digital-analogue conversion; echo suppression; 1.5 micron; A/D converter; CMOS device; analog hybrid; codecs; digital echo cancellation; encoder SNR performance; programmable digital balance filter; sigma-delta modulation; signal-to-noise performance; single-power-supply; Analog-digital conversion; Circuits; Codecs; Decoding; Digital filters; Digital signal processing; Echo cancellers; Filtering; Finite impulse response filter; Helium;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.58290

Filename

58290