Title :
CMOS tapered buffer
Author :
Li, N.V. ; Haviland, Gene L. ; Tuszynski, A.A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
fDate :
8/1/1990 12:00:00 AM
Abstract :
Jaeger´s buffer comprises a string of tapered inverters. Each inverter is molded by a capacitor and a conductor. In this work, the capacitor is split into inherent and load components (Cx and Cy), and it is shown that the value of the optimal taper depends on the Cx/Cy ratio: the best taper exceeds Jaeger´s 2.72 slope, but only moderately
Keywords :
CMOS integrated circuits; buffer circuits; equivalent circuits; integrated logic circuits; logic design; CMOS; fan-out decision; logic device buffer; split capacitor model; tapered buffer; tapered inverters; BiCMOS integrated circuits; CMOS logic circuits; Capacitance; Capacitors; Conductors; Inverters; Logic devices; MOSFETs; Semiconductor device modeling; Solid state circuits;
Journal_Title :
Solid-State Circuits, IEEE Journal of
