Simple noise model and low-noise data-output buffer for ultrahigh-speed memories

Author

Wada, Tomohisa ; Eino, Masanao ; Anami, Kenji

Author_Institution

Mitsubishi Electr. Corp., Hyogo, Japan

Volume

25

Issue

6

fYear

1990

fDate

12/1/1990 12:00:00 AM

Firstpage

1586

Lastpage

1588

Abstract

An analytic noise (voltage bounce on chip-internal V_CC/GND lines) model for data-output buffers is described. The model indicates that t_r (switching time of output transistor) greater than L×G₀ (product between the parasitic inductance on V_CC/GND lines and the conductance of the output transistor) and small output voltage amplitude are required in order to reduce the noise voltage. The model give VLSI circuit designers a rough estimation of the V_CC/CND line noise. A low-noise data-output buffer combined with a voltage down converter (VDC) is proposed. It decreases the peak noise voltage by one-half without degrading the access time

Keywords

VLSI; buffer circuits; electron device noise; integrated memory circuits; VLSI circuit design; chip-internal V_CC/GND lines; data-output buffer; low-noise; noise model; output transistor; parasitic inductance; switching time; ultrahigh-speed memories; voltage down converter; Circuit noise; Circuit simulation; Degradation; Inductance; Kirchhoff´s Law; Noise generators; Noise level; Noise reduction; Very large scale integration; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.62195

Filename

62195