• DocumentCode
    1543090
  • Title

    SFQ data processing with set/reset information

  • Author

    Kodaka, H. ; Hosoki, T. ; Kitagawa, M. ; Okabe, Y.

  • Author_Institution
    Res. Center for Adv. Sci. & Technol., Tokyo Univ., Japan
  • Volume
    9
  • Issue
    2
  • fYear
    1999
  • fDate
    6/1/1999 12:00:00 AM
  • Firstpage
    3729
  • Lastpage
    3732
  • Abstract
    We propose a new class of SFQ logic circuits. In this new approach, an SFQ pulse represents the transition between "zero" and "one". By using these two bits of information, a one-to-one correspondence between input and output can be realized. Since the correspondence is then the same as in semiconductor circuits, this method permits logic design without clock elements. In order to carry out this logic, we propose the most fundamental element, a new DC/SFQ converter. A computer simulation and low-speed test were performed. Both results showed that this converter operates correctly with a wide margin. Moreover, this converter also provides the basis for many other logic elements such as AND, OR, and XOR.
  • Keywords
    circuit simulation; combinational circuits; integrated circuit testing; logic simulation; superconducting device testing; superconducting logic circuits; DC/SFQ converter; SFQ data processing; logic circuits; logic design; logic elements; low-speed test; one-to-one correspondence; set/reset information; CMOS logic circuits; CMOS process; Clocks; Data processing; Logic circuits; Logic design; Logic devices; Quantum computing; Timing; Voltage;
  • fLanguage
    English
  • Journal_Title
    Applied Superconductivity, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1051-8223
  • Type

    jour

  • DOI
    10.1109/77.783838
  • Filename
    783838