Self-timed parallel adders based on DI RSFQ primitives

Author

Kameda, Y. ; Polonsky, S.V. ; Maezawa, M. ; Nanya, T.

Author_Institution

Res. Center for Adv. Sci. & Technol., Tokyo Univ., Japan

Volume

9

Issue

2

fYear

1999

fDate

6/1/1999 12:00:00 AM

Firstpage

4040

Lastpage

4045

Abstract

We present two versions of self-timed pipelined parallel carry-look-ahead adders. The adders are designed based on delay-insensitive (DI) rapid single-flux-quantum (RSFQ) primitives. Basic binary gates employ dual-rail encoded data, which include timing information in themselves. One version uses wave pipelining and the other delay-insensitive pipelining with a request-acknowledge data transfer protocol. We show simulation results of 4 to 32-bit adders and their sensitivity to delay variations. Two design schemes are compared in terms of area, speed, robustness, interface and design process for large systems.

Keywords

adders; asynchronous circuits; parallel processing; pipeline arithmetic; superconducting logic circuits; timing circuits; 4 to 32 bit; DI RSFQ primitive; asynchronous circuit; delay-insensitive pipelining; delay-insensitive rapid single-flux-quantum circuit; dual-rail binary gate; request-acknowledge data transfer protocol; self-timed pipelined parallel carry-look-ahead adder; simulation; superconductive Josephson junction device; ultrafast digital design; wave pipelining; Adders; Clocks; Delay; Interferometers; Josephson junctions; Pipeline processing; Pulse circuits; Timing; Voltage; Wires;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/77.783914

Filename

783914