Design investigation of 1D-arrays of metallic single electron tunneling transistors

Starting from the geometry and material constants we calculate the capacitances in metallic single charge tunneling structures using a 3D numerical field computation tool based on the boundary element method. This is exemplified by means of a step-edge cut-off tunnel junction geometry. Beginning with a single junction we further investigate multi-junction single electron transistors and, for the first time, arrays of them. Beside this calculation of the intercapacitance matrix we quantitatively analyze the influence of parasitic background charges. In view of its performance our tool could establish the basis for the evaluation of more complex layouts in single charge electronics.