Simulation and 18 Gb/s testing of a data-driven self-timed RSFQ demultiplexer

Author

Yoshikawa, N. ; Deng, Z.J. ; Whiteley, S.R. ; Van Duzer, T.

Author_Institution

Fac. of Eng., Yokohama Nat. Univ., Japan

Volume

9

Issue

2

fYear

1999

fDate

6/1/1999 12:00:00 AM

Firstpage

4349

Lastpage

4352

Abstract

We have developed a data-driven self-timed (DDST) rapid-single-flux-quantum (RSFQ) demultiplexer (demux) for the interface between on-chip high-speed RSFQ circuits and off-chip low-speed circuits. In order to eliminate the timing issue in a synchronous clocking system we employed the DDST architecture, where a clock signal is localized within a 2-bit basic demux module and dual rail lines are used to transfer the timing information between the modules. A larger demux can be produced simply by connecting the 2-bit modules in a tree structure. The DDST demux was designed for 10 Gb/s operation with sufficient dc bias margin using HYPRES 1 kA/cm/sup 2/ Nb process. We have successfully tested operation of the 2-bit demux up to 18 GHz using the DDST on-chip high-speed test system which was developed in our group.

Keywords

clocks; demultiplexing equipment; high-speed integrated circuits; niobium; superconducting logic circuits; timing; 18 Gbit/s; HYPRES process; Nb; clock signal; data-driven self-timed RSFQ demultiplexer; dc bias margin; dual rail lines; off-chip low-speed circuits; on-chip high-speed RSFQ circuits; synchronous clocking system; timing issue; tree structure; Automatic testing; Circuit simulation; Circuit testing; Clocks; Joining processes; Niobium; Rail transportation; System testing; Timing; Tree data structures;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/77.783988

Filename

783988