DocumentCode :
1544380
Title :
Estimating error rates in processor-based architectures
Author :
Rezgui, Sana ; Velazco, Raoul ; Ecoffet, Robert ; Rodriguez, Santiago ; Mingo, José Ramon
Author_Institution :
TIMA Lab., Grenoble, France
Volume :
48
Issue :
5
fYear :
2001
fDate :
10/1/2001 12:00:00 AM
Firstpage :
1680
Lastpage :
1687
Abstract :
The paper investigates a new technique to predict error rates in digital architectures based on microprocessors. Three studied cases are presented concerning three different processors. Two of them are included in the instruments of a satellite project. The actual space applications of these two instruments were implemented using the capabilities of a dedicated system. Results of the fault injection and radiation testing experiments and discussions about the potentialities of this technique are presented
Keywords :
aerospace computing; aerospace testing; computer architecture; computer testing; microcomputers; digital architectures; error rate estimation; fault injection; microprocessor; processor-based architectures; radiation testing; satellite project; space application; Circuit faults; Circuit testing; Error analysis; Helium; Instruments; Laboratories; Microprocessors; Satellites; Single event upset; Space vehicles;
fLanguage :
English
Journal_Title :
Nuclear Science, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9499
Type :
jour
DOI :
10.1109/23.960357
Filename :
960357
Link To Document :
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