• DocumentCode
    1544600
  • Title

    Using a multiple storage quad tree on a hierarchical VLSI compaction scheme

  • Author

    Hsiao, Pei-Yung ; Feng, Wu-Shiung

  • Author_Institution
    Grad. Inst. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • Volume
    9
  • Issue
    5
  • fYear
    1990
  • fDate
    5/1/1990 12:00:00 AM
  • Firstpage
    522
  • Lastpage
    536
  • Abstract
    A graph-generating algorithm and the experimental results of a hierarchical mask-layout-compaction scheme based on a plane-sweep algorithm, a fast region-query and a space-efficient data structure called the hierarchical multiple-storage quad tree are presented. For a mask-layout design, a rectangle is used as the primary element of the layout. Hence, in the hierarchical mask-compaction scheme, the graph-generating algorithm is based on the edges of rectangles rather than the central lines of symbols for the symbolic-compaction design. The plane-sweep algorithm is also called a dynamic event scheduling algorithm and can be applied to solve some other problems in the field of computational geometry and image processing. The efficiencies of the plane-sweep algorithm and the graph-generating algorithm are dependent on the region-query operations of the spatial data structure. By using the improved multiple storage quad tree as the spatial data structure in the system, the mask-layout compactor has been accomplished in a practically linear time performance in terms of the rectangles in the source layout
  • Keywords
    VLSI; circuit layout CAD; data structures; integrated circuit technology; trees (mathematics); dynamic event scheduling algorithm; fast region-query; graph-generating algorithm; hierarchical VLSI compaction scheme; mask-layout design; multiple storage quad tree; plane-sweep algorithm; space-efficient data structure; spatial data structure; Algorithm design and analysis; Capacitive sensors; Compaction; Computational geometry; Data structures; Image processing; Scheduling algorithm; Tree data structures; Tree graphs; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.55182
  • Filename
    55182