• DocumentCode
    1544862
  • Title

    Evaluation and optimization of replication algorithms for logic bipartitioning

  • Author

    Enos, Morgan ; Hauck, Scott ; Sarrafzadeh, Majid

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
  • Volume
    18
  • Issue
    9
  • fYear
    1999
  • fDate
    9/1/1999 12:00:00 AM
  • Firstpage
    1237
  • Lastpage
    1248
  • Abstract
    Logic partitioning is an important area of very large scale integration computer aided design and there have been numerous approaches proposed. Logic replication, the duplication of logic in order to minimize communication between partitions, can be an effective component of a complete partitioning solution. In this paper we seek a better understanding of the important issues in logic replication. By adding new optimizations to existing algorithms we are able to significantly improve the quality of these techniques, achieving up to 13.9% better results than the best existing replication techniques. When integrated into our already state-of-the-art (nonreplication) partitioner, we improve overall cutsizes by 38.8%, while requiring the duplication of at most 7% of the logic
  • Keywords
    VLSI; circuit CAD; circuit optimisation; integrated circuit design; logic CAD; logic partitioning; network topology; computer aided design; logic bipartitioning; logic replication; optimizations; overall cutsizes; replication algorithms; very large scale integration; Application specific integrated circuits; Design automation; Field programmable gate arrays; Heuristic algorithms; Integrated circuit yield; Logic design; Logic devices; Partitioning algorithms; Prototypes; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.784117
  • Filename
    784117