DocumentCode :
1544922
Title :
Analog testing by characteristic observation inference
Author :
Lindermeir, Walter M. ; Graeb, Helmut E. ; Antreich, Kurt J.
Author_Institution :
Infineon Technol., Munich, Germany
Volume :
18
Issue :
9
fYear :
1999
fDate :
9/1/1999 12:00:00 AM
Firstpage :
1353
Lastpage :
1368
Abstract :
This paper presents a new approach to the test design of analog circuits, called characteristic observation inference (COI). The COI method considers parametric as well as catastrophic faults. A strict distinction between the operational environment, defined by the specifications of the circuit, and the test environment, defined by the test configuration and the test equipment, is introduced. A parametric fault model is developed that combines circuit specifications, statistical parameters reflecting parametric faults, and measurements of the circuit under test. These measurements are called characteristic observations. For each specification, a test inference criterion is computed using feature extraction and logistic discrimination analysis. From a set of such criteria the satisfaction or violation of the specifications can be inferred from characteristic observations. Based on these results, additional test criteria for catastrophic faults are determined using test set compaction. Moreover, measurement noise and parasitic effects, which crucially influence the test design, are systematically considered, and a physically interpretable sampling strategy is presented. The COI method applied to two different test designs yields very good results with respect to parametric faults as well as to catastrophic faults
Keywords :
analogue integrated circuits; fault diagnosis; feature extraction; integrated circuit testing; integrated circuit yield; test equipment; catastrophic faults; characteristic observation inference; circuit specifications; feature extraction; measurement noise; operational environment; parametric faults; parasitic effects; physically interpretable sampling strategy; statistical parameters; test configuration; test design; test environment; test equipment; test set compaction; Analog circuits; Circuit faults; Circuit testing; Compaction; Feature extraction; Logistics; Noise measurement; Sampling methods; System testing; Test equipment;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.784126
Filename :
784126
Link To Document :
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