A multigigahertz clocking scheme for the Pentium(R) 4 microprocessor

Author

Kurd, Nasser A. ; Barkarullah, J.S. ; Dizon, Rommel O. ; Fletcher, Thomas D. ; Madland, Paul D.

Author_Institution

Intel Corp., Hillsboro, OR, USA

Volume

36

Issue

11

fYear

2001

fDate

11/1/2001 12:00:00 AM

Firstpage

1647

Lastpage

1653

Abstract

Core and I/O clock design for the Pentium(R) 4 microprocessor is described. Two phase-locked loops generate core and I/O clocks supporting concurrent multiple frequencies. A clock distribution network with skew optimization and jitter reduction is designed to achieve low clock inaccuracies for processors at frequencies ⩾2 GHz for the core and ⩾4 GHz for the rapid execution engine. A global medium clock frequency is distributed. Local clock drivers generate pulsed or regular (nonpulsed) clocks at fast, medium, and slow frequencies. A 3.2-GB/s system bus is achieved using a dedicated I/O phase-locked loop with glitch protection and detection. Silicon speed path tools and clock debug features are designed to enable a short debug cycle

Keywords

circuit optimisation; clocks; computer debugging; digital phase locked loops; driver circuits; integrated circuit design; microprocessor chips; timing jitter; 2 GHz; 3.2 GB/s; 4 GHz; I/O clock design; Pentium 4 microprocessor; clock debug features; clock distribution network; clock inaccuracies; concurrent multiple frequencies; core design; debug cycle; dedicated I/O phase-locked loop; glitch detection; glitch protection; global medium clock frequency; jitter reduction; local clock drivers; multigigahertz clocking scheme; nonpulsed clocks; phase-locked loops; pulsed clocks; rapid execution engine; skew optimization; Clocks; Design optimization; Engines; Frequency; Jitter; Microprocessors; Phase locked loops; Protection; Pulse generation; System buses;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.962284

Filename

962284