A 150-MHz graphics rendering processor with 256-Mb embedded DRAM

Author

Khan, Aurangzeb K. ; Magoshi, Hidetaka ; Matsumoto, Tadashi ; Fujita, Jun-Ichi ; Furuhashi, Makoto ; Imai, Masatoshi ; Kurose, Yoshikazu ; Sato, Morio ; Sato, Katsuhiko ; Yamashita, Yujiro ; Kwan, Kinying ; Le, Duc-Ngoc ; Yu, John H. ; Nguyen, Trung ; Yan

Author_Institution

Simplex Solutions Inc., Sunnyvale, CA, USA

Volume

36

Issue

11

fYear

2001

fDate

11/1/2001 12:00:00 AM

Firstpage

1775

Lastpage

1784

Abstract

A 150-MHz graphics rendering processor with an integrated 256-Mb embedded DRAM, delivering a rendering rate of 75 M polygons/s, is presented, 287.5 M transistors are integrated on a 21.3×21.7 mm ² die in a 0.18-μm embedded DRAM CMOS process with six layers of metal. Design methodologies for hierarchical electrical and physical design of this very large-scale IC, including power distribution, fully hierarchical timing design, and verification utilizing a newly developed nonlinear model, clock design, propagation delay, and crosstalk noise management in multi-millimeter RC transmission lines, are presented

Keywords

CMOS digital integrated circuits; VLSI; coprocessors; crosstalk; delays; integrated circuit design; integrated circuit modelling; low-power electronics; rendering (computer graphics); timing; 0.18 micron; 150 MHz; 256 Mbit; CMOS process; crosstalk noise management; embedded DRAM; fully hierarchical timing design; graphics rendering processor; hierarchical electrical design; multi-millimeter RC transmission lines; nonlinear model; physical design; power distribution; propagation delay; rendering rate; very large-scale IC; CMOS process; Design methodology; Graphics; Integrated circuit modeling; Integrated circuit noise; Large-scale systems; Power distribution; Random access memory; Rendering (computer graphics); Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.962301

Filename

962301