Title :
Two-Dimensions Vernier Time-to-Digital Converter
Author :
Vercesi, Luca ; Liscidini, Antonio ; Castello, Rinaldo
Author_Institution :
Lab. di Microelettronica, Univ. degli Studi di Pavia, Pavia, Italy
Abstract :
A two-dimensions Vernier algorithm applied to a time to digital converter (TDC) is presented. The solution proposed minimizes the length of the delay lines used to perform the digital conversion leading to a better efficiency compared to traditional linear approaches. A 7-bits TDC prototype, targeted for all digital PLL application, was realized in 65 nm CMOS technology with a time resolution of 4.8 ps and a power consumption of 1.65 mW for a conversion rate of 50 Msps. The longest delay line used in such a prototype is one third than what would have been required for a standard Vernier TDC.
Keywords :
CMOS integrated circuits; phase locked loops; CMOS technology; TDC prototype; Vernier algorithm; digital PLL application; power 1.65 mW; size 65 nm; time to digital converter; CMOS technology; Delay effects; Delay lines; Energy consumption; Interpolation; Jitter; Phase locked loops; Phase noise; Prototypes; Quantization; All digital PLL; TDC calibration; Vernier; time to digital converter;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2010.2047435
