A 58.9-dB ACR, 85.5-dB SBA, 5–26-MHz Configurable-Bandwidth, Charge-Domain Filter in 65-nm CMOS

A configurable-bandwidth charge-domain filter (CDF) with bandwidth calibration and clock-pulse modulation (CPM) is proposed. The bandwidth calibration scheme controls the insertion loss at a pre-specified frequency by modulating the feedback gain and delay; this helps the CDF to suppress the sinc distortion and thus achieve near-ideal brick-wall filtering. For multi-frequency compensation, a multi-stage CDF architecture is utilized to organize the feedback delay. Together with non-decimation filtering, the noise folding effect as well as the chip area can be reduced. On the other hand, to provide a stable gain under variable channel bandwidth, a CPM scheme is proposed; it adjusts the clock period with a fixed pulse width by zero-insertion. Implemented in a 65-nm CMOS technology, the proposed CDF achieves 58.9-dB adjacent-channel rejection (ACR), 85.5-dB stop-band attenuation (SBA), 41-dB conversion gain, and 19.5-MHz channel bandwidth at 320-MS/s input-sampling rate. Furthermore, for input-sampling rates range from 300 to 480 MS/s, the channel bandwidth can be configured from 5 to 26 MHz. At 1.2-V supply, the chip consumes 8.4-mW power and occupies 0.52-mm² area.