Title :
A realistic fault model and test algorithms for static random access memories
Author :
Dekker, Rob ; Beenker, Frans ; Thijssen, Loek
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
fDate :
6/1/1990 12:00:00 AM
Abstract :
Testing static random access memories (SRAMs) for all possible failures is not feasible and one must restrict the class of faults to be considered. This restricted class is called a fault model. A fault model for SRAMs based on physical spot defects, which are modeled as local disturbances in the layout of the SRAM, is presented. Two linear test algorithms that cover 100% of the faults under the fault model are proposed. A general solution is given for testing word-oriented SRAMs. The practical validity of the fault model and the two test algorithms are verified by a large number of actual wafer tests and device failure analyses
Keywords :
fault location; integrated circuit testing; integrated memory circuits; random-access storage; SRAMs; fault model; physical spot defects; static random access memories; test algorithms; wafer tests; Circuit faults; Decoding; Failure analysis; Logic arrays; Random access memory; Read-write memory; SRAM chips; Semiconductor device modeling; Silicon; Testing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
