Design-for-reusability in VHDL

The reuse of electronic components can improve productivity in system design. However, without careful planning, components are rarely designed for reuse. Hardware description languages are commonly used to construct from simple hardware to complex ones. HDLs allow the creation of reusable models, but the reusability of a design does not come with language features alone. It requires design disciplines to reach an efficient reusable design. Reusability issues and design methodologies to achieve design-for-reusability (DFR) are presented. Results of measuring the reusability of ten VHDL applications, based on the proposed reusable models, are summarised. This research allows us to gain an insight into DFR.