DocumentCode :
1546535
Title :
A 7-Bit 18th Order 9.6 GS/s FIR Up-Sampling Filter for High Data Rate 60-GHz Wireless Transmitters
Author :
Muller, Jonathan ; Stefanelli, Bruno ; Frappe, Antoine ; Ye, Lu ; Cathelin, Andreia ; Niknejad, Ali ; Kaiser, Andreas
Author_Institution :
STMicroelectron., Crolles, France
Volume :
47
Issue :
7
fYear :
2012
fDate :
7/1/2012 12:00:00 AM
Firstpage :
1743
Lastpage :
1756
Abstract :
This paper presents the design and measurement of a 4 × oversampled 18th order digital low-pass FIR filter. It is a key building block in the proposed digitally enhanced transmitter architecture for 60 GHz wireless high-data rate links. Spectrum mask requirements are fully satisfied for OFDM modulated signals without requiring additional analog filtering. Pipelined CPL adders and TSPC flip-flops are used to enable a very high operation frequency. The core area is 0.1 mm2 in a standard GP 65 nm CMOS process. Measured power consumption is 400 mW at 9.6 GS/s with a 1.4 V power supply voltage.
Keywords :
CMOS digital integrated circuits; FIR filters; OFDM modulation; flip-flops; millimetre wave devices; radio links; radio transmitters; 18th order digital low-pass FIR filter; FIR up-sampling filter; GP CMOS process; OFDM modulated signals; TSPC flip-flops; additional analog filtering; digitally enhanced transmitter architecture; frequency 60 GHz; high data rate wireless transmitters; high operation frequency; pipelined CPL adders; power 400 mW; power consumption; power supply voltage; spectrum mask requirements; voltage 1.4 V; wireless high-data rate links; Adders; Attenuation; Bandwidth; Finite impulse response filter; OFDM; Radio transmitters; Standards; CMOS; Digital FIR Filter; millimeter waves; transmitter;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2012.2191677
Filename :
6222364
Link To Document :
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