SRAM bitline circuits on PD SOI: advantages and concerns

Author

Kuang, Jente B. ; Ratanaphanyarat, Somnuk ; Saccamango, Mary Jo ; Hsu, Louis L C ; Flaker, Roy C. ; Wagner, Lawrence F. ; Chu, S-f Sanford ; Shahidi, Ghavam G.

Author_Institution

Microelectron. Div., IBM Corp., Hopewell Junction, NY, USA

Volume

32

Issue

6

fYear

1997

fDate

6/1/1997 12:00:00 AM

Firstpage

837

Lastpage

844

Abstract

This paper presents a study of sub-0.25-μm CMOS SRAM bitline circuitry on partially depleted (PD) silicon-on-insulator (SOI) technology. SOI implementations outperform conventional bulk ones due to significant reduction of collective device junction capacitance on the bitlines. Floating body effects are investigated for both read and write cycles. Array content dependent behaviors are identified for the first time and analyzed with worst-case temporal and spatial pattern combinations

Keywords

CMOS memory circuits; SRAM chips; silicon-on-insulator; 0.25 micron; CMOS SRAM bitline circuit; PD SOI; array content; collective device junction capacitance; floating body effect; partially depleted silicon-on-insulator technology; spatial pattern; temporal pattern; CMOS technology; Capacitance; Circuit noise; Circuit topology; Microelectronics; Random access memory; Research and development; Silicon on insulator technology; Threshold voltage; Voltage control;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.585285

Filename

585285