Are you ready for next-generation dynamic RAM chips?

The problems faced in developing 64 Mb DRAMs (dynamic RAMs), which will be required for the more powerful computers of the future, are examined. One of these is array noise, the unwanted disturbance in a memory IC generated by the normal movement of data within the array. Three approaches to the problem are described: the twisted bit line, shielding the bit lines from each other by placing the cell capacitor between them, and reducing the number of activated work lines (and therefore the number of activated bit lines). Their advantages and disadvantages are discussed. Getting sufficient cell capacitance into the available cell area is a major problem, as neither the simple trench capacitor, which is a capacitor buried in a trench hole, nor the simple stacked capacitor, a configuration in which the capacitor is stacked above the transistor, can satisfy the demands imposed by the 64 Mb DRAM. Modifications of the stacked-capacitor approach, which appears to be the most promising line of attack at present, are described.<>