Title :
A comprehensive study of performance and reliability of P, As, and hybrid As/P nLDD junctions for deep-submicron CMOS logic technology
Author :
Nayak, D.K. ; Ming-Yin Hao ; Umali, J. ; Rakkhit, R.
Author_Institution :
Logic Technol. Div., Adv. Micro Devices Inc., Sunnyvale, CA, USA
fDate :
6/1/1997 12:00:00 AM
Abstract :
A comprehensive study of P, As, and hybrid As/P nLDD junctions is presented in terms of performance, reliability, and manufacturability for the first time. It is found that As junctions limit the performance of deep submicron devices due to unacceptable hot-carrier reliability, whereas a hybrid junction (light dose P added to medium dose As) dramatically improves hot-carrier reliability while maintaining high performance and manufacturability. For L/sub eff/ of 0.19 μm, using this hybrid junction in a manufacturing process, an inverter gate delay of 32 ps, dc hot carrier life time exceeding ten years, and off-state leakage below 30 pA/μm at 2.9 V have been achieved.
Keywords :
CMOS logic circuits; carrier lifetime; delays; hot carriers; integrated circuit manufacture; integrated circuit measurement; integrated circuit reliability; ion implantation; leakage currents; logic gates; 0.19 mum; 2.9 V; 32 ps; Si:As; Si:As,P; Si:P; dc hot carrier life time; deep-submicron CMOS logic technology; hot-carrier reliability; hybrid junction; inverter gate delay; manufacturability; nLDD junction performance; nLDD junction reliability; off-state leakage; CMOS logic circuits; CMOS technology; Delay effects; Hot carriers; Hybrid junctions; Implants; Isolation technology; Maintenance; Manufacturing; Ring oscillators;
Journal_Title :
Electron Device Letters, IEEE
