Direct digital synthesizer with jittered clock

Since the direct digital synthesizer (DDS) can potentially be used as a flexible clock source, it is of interest to study its spectrum purity as well as jitter characteristic. In this paper, we investigate the jitter transfer characteristic of the DDS clock driven by a jittered digital-to-analog converter (DAC) clock. We first derive the dosed form expressions of the spectrum of the DAC output signal with jittered driving clock. These expressions are then used to investigate the spectral structure of the DDS clock. Equations are derived for the calculation of the SNR. For a small phase noise power in the driving clock, the DDS clock SNR is obtained in a simple closed form and is shown to be lower than that of the input driving clock by the amount of 20 log(f_s/d_d) dB, where f_s is the nominal driving clock frequency and f_d is the desirable DDS output clock frequency