DocumentCode :
1547553
Title :
Low power state assignment and flipflop selection for finite state machine synthesis - a genetic algorithmic approach
Author :
Chattopadhyay, S.
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Guwahati, India
Volume :
148
Issue :
45
fYear :
2001
Firstpage :
147
Lastpage :
151
Abstract :
Current renewed emphasis for more aggressive logic designs with lesser area, delay, and power, demands exploration of alternative avenues that could lead to better designs, albeit at the higher cost of computation. The author explores the avenue of genetic algorithms for a holistic view for synthesis of finite state machines (FSM) targeting power reduction by incorporating both state assignment and sequential element selection. Exhaustive experimentation performed on a large suite of benchmarks has established the fact that this tool results in state encodings with on average 46.08% reduction in power requirement over NOVA, without any significant increase in the number of product terms. The effectiveness of judicious flipflop, selection has been demonstrated by showing that the approach with all D-flipflops as the sequential element requires 33.78% more power than the approach with a choice of D and T flipflop types. Moreover, as compared to the technique presented in LPSA, the algorithm presented requires 38.96% less power when using a mix of D and T flipflops. The quality of the solution obtained and the high rate of convergence have established the effectiveness of the genetic algorithm in solving this particular NP-complete problem. Further, the inherent parallelism of genetic algorithms makes the proposed scheme ideal for solving the problem in a multiprocessor environment
Keywords :
circuit CAD; computational complexity; finite state machines; flip-flops; genetic algorithms; logic CAD; state assignment; D-flipflops; FSM; LPSA; NOVA; NP-complete problem; T flipflop types; aggressive logic designs; finite state machine synthesis; flipflop selection; genetic algorithmic approach; higher computation cost; holistic view; inherent parallelism; low power state assignment; multiprocessor environment; power reduction; power requirement; product terms; sequential element; sequential element selection; state assignment; state encodings;
fLanguage :
English
Journal_Title :
Computers and Digital Techniques, IEE Proceedings -
Publisher :
iet
ISSN :
1350-2387
Type :
jour
DOI :
10.1049/ip-cdt:20010666
Filename :
963470
Link To Document :
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