An efficient pipelined parallel architecture for blocking effect removal in HDTV

This paper presents an efficient architecture for blocking effect removal in HDTV. Since there is a large amount of image signal for processing in digital HDTV, the memory size and fast operation have been the main concerns of the DSP (digital signal processing) architectures. To reduce the size of the memory, the memory is partitioned into many memory banks. This makes it possible to access the memory concurrently. Also, to improve the operation speed, a pipelined parallel architecture and a memory scheduling technique are adopted. Since multiplications and divisions are time-critical, these operations are replaced with shiftings. Therefore this architecture is very fast and uses small size memory banks, and this makes it possible to realize a real-time signal processor