Simulating process-induced gate oxide damage in circuits

Author

Tu, Robert ; King, Joseph C. ; Shin, Hyungcheol ; Hu, Chenming

Author_Institution

Adv. Micro Devices Inc., Sunnyvale, CA, USA

Volume

44

Issue

9

fYear

1997

fDate

9/1/1997 12:00:00 AM

Firstpage

1393

Lastpage

1400

Abstract

Advanced processing techniques such as plasma etching and ion implantation can damage the gate oxides of MOS devices and thus pose a problem to circuit reliability. In this paper, we present a simulator which predicts oxide failure rates during and after processing and pinpoints strong charging current locations in the layout where changes can be made to improve circuit hot-carrier reliability. We present the models and experimental results used to develop the simulator and demonstrate the usefulness of this simulator

Keywords

MOS integrated circuits; circuit analysis computing; electric breakdown; failure analysis; hot carriers; integrated circuit reliability; ion implantation; sputter etching; MOS devices; charging current locations; circuit reliability; circuit simulator; hot-carrier reliability; ion implantation; oxide failure rates; plasma etching; process-induced gate oxide damage; Circuit simulation; Etching; Ion implantation; MOS devices; Plasma applications; Plasma devices; Plasma immersion ion implantation; Plasma materials processing; Plasma simulation; Predictive models;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.622593

Filename

622593